Category: Xilinx Ultrascale

EL2 virtualization on Zynq Ultrascale+ notes

Exception Levels: Execution States: Security State Service Call Routing: Hypervisor mode executes at EL2 in the AArch32 state. EL2 is implemented only in a non-secure state, to support guest operating system management. EL2 virtualization provides: virtual values for the contents of a small number of identification registers traps for EL2 exceptions (a hypervisor might be…

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Ultrascale+ PL Full/Partial configuration

Using Processor Configuration Access Port (PCAP) Device tree overlays are not supported by Xilinx DTG and must be hand-crafted Kernel configuration is required Note, partial reconfiguration of the PL regions requires partioning of the bitstream into blocks so that they can be replaced as part of a higher level bitstream design. As far as I…

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